1. Field of the Invention
The present invention relates to a system on chip, and more particularly to a system on chip including an image processing memory with multiple access.
2. Description of Related Art
Sub-systems in a conventional system on chip may be divided into a plurality of power domains, and the sub-systems in the respective power domains may be powered individually.
FIG. 1 is a block diagram illustrating a conventional system on chip including a plurality of sub-systems.
Referring to FIG. 1, the conventional system on chip includes a plurality of sub-systems. Each of the sub-systems includes a central processing unit (CPU) sub-system 20, an audio sub-system 30, an image sub-system 40, a digital signal processor (DSP) sub-system 50, an input/output (IO) sub-system 60 and a communication sub-system 70. The sub-systems 20, 30, 40, 50, 60 and 70 are respectively connected to a system bus 10. The sub-systems 20, 30, 40, 50, 60 and 70 are divided into power domains according to a function, an operating time, a schedule of the system on chip, etc. A sub-system that is not operated enters a power-down mode to decrease power consumption. The sub-systems 20, 30, 40, 50, 60 and 70 in FIG. 1 may respectively correspond to each power domain.
FIG. 2 is a diagram illustrating a configuration of the image sub-system in the system on chip of FIG. 1.
Referring to FIG. 2, the image sub-system 40 includes an image processing logic 45 and an image processing memory 47. The image processing memory 47 is accessed only through the image processing logic 45. The image processing memory 47 is included in a power domain including the image processing logic 45. The image sub-system 40 enters a power-down mode when the image processing logic 45 does not perform an image processing such as taking a picture, a JPEG coding, etc. The image processing memory 47 is only used for the image processing because the image processing memory 47 also enters a power-down mode when a power-down operation is performed on the image sub-system 40 to enter the power-down mode.
In performing the image processing, a memory size is determined according to a resolution of an image. The image processing is performed by block unit or line unit and memory size may be determined according the unit (block or line). The memory size that is needed to perform the operation with data of block unit or line unit is similar to an internal memory size of another module or a sub-system in the system on chip.
The memory used for the image processing needs 607,168 bits of RAM when an internal memory size is 524,524,288 bits and a DSP needs 786,432 bits of DRAM. That is, the memory size used for the image processing is similar to the internal memory size of module or the sub-system. In the case of conventional system on chip, the image processing memory may not be used when the image processing logic 45 is not operated because the image processing logic 45 and the image processing memory 47 are included in the same power domain.
FIG. 3 is a block diagram illustrating another conventional system on chip including a memory sub-system.
Referring to FIG. 3, the system on chip includes a memory sub-system 80 and a plurality of sub-systems 20, 30, 40, 50 and 70. The memory sub-system 80 includes a data RAM 82, a program ROM 84 and a program RAM 86. The memory sub-system 80 is accessed by the sub-systems 20, 30, 40, 50 and 70 through a system bus 10. An image processing memory may not be used when the image sub-system 40 is in a power-down mode and the system on chip needs to access an external memory (not shown) when a capacity of the sub-system 80 is insufficient. The access to the external memory significantly degrades performance of the system because a path for accessing to the external memory is typically heavily loaded.
Therefore, a need exists for a system on chip including an image processing memory with multiple access.